The present invention relates to telecommunications systems, and more particularly to SONET path/ATM physical layer transmit/receive processors implemented as application specific integrated circuits (ASICs) to provide a greatly increased data rate.
A SONET frame may be thought of as a three-dimensional array of bytes, or a data block, having length, width and depth. The length and width are referenced as rows and columns (9.times.90), and the depth is a number of pages determined by data width (48 for OC-48). The data rate is 125 microseconds per block. The first three columns, all rows and pages, are used for overhead management of the SONET frame, with a pointer at a known location within such overhead management data. The pointer indicates another column within the SONET frame that is one column wide, encompasses all rows and is one-third the depth of the SONET frame, with only the first page column containing path overhead data (the rest being stuffed). Thus it is one page deep for OC-1 and OC-3c and 16 pages deep for OC-48c. The SONET frame is a synchronized frame, the beginning of which may be indicated by a frame pulse.
ATM is an asynchronous data transmission system that is composed of 53-byte structures, referred to as cells. Each cell has a four-byte header and a one-byte header error checksum followed by 48 bytes of data. The ATM cells are inserted into the SONET frame for transport at contiguous locations excepting those locations reserved for frame and path overhead, as discussed above. Currently there exist OC-12 processors with 8-bit SONET and 16-bit ATM UTOPIA interfaces, i.e., a maximum depth of 12 pages, that provide a 622 Mb/sec data rate.
What is desired is a SONET path/ATM physical layer transmit/receive processor implementable on an ASIC that provides OC-48 capability, i.e., a data rate of 2.488 Gb/sec.